IRVINE Out - of - order Parallel Discrete Event Simulation

OF THE DISSERTATION Out-of-order Parallel Discrete Event Simulation for Electronic System-Level Design By Weiwei Chen Doctor of Philosophy in Electrical and Computer Engineering University of California, Irvine, 2013 Professor Rainer Doemer, Chair The large size and complexity of the modern embedded systems pose great challenges to design and validation. At the so called electronic system level (ESL), designers start with a specification model of the system and follow a systematic top-down design approach to refine the model to lower abstraction levels step-by-step by adding implementation details. ESL models are usually written in C-based System-level Description Languages (SLDLs), and contain the essential features, such as clear structure and hierarchy, separate computation and communication, and explicit parallelism. The validation of ESL models typically relies on simulation. Fast yet accurate simulation is highly desirable for efficient and effective system design. In this dissertation, we present out-of-order parallel discrete event simulation (OoO PDES), a novel approach for efficient validation of system-level designs by exploiting the parallel capabilities of todays multi-core PCs for system level description languages. OoO PDES breaks the global simulation-cycle barrier of traditional DE simulation by localizing the simulation time into each thread, carefully delivering notified events, and handling a dynamic management of simulation sets. Potential conflicts caused by parallel accesses to shared variables and out-oforder thread scheduling are prevented by an advanced predictive static model analyzer in the